/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HC32F4A0_REGS_SRAM_H
#define __HC32F4A0_REGS_SRAM_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include "core/include/hc32f4a0_regs_base.h"
#include "common/hc32f4a0_common.h"

/* \brief SRAM 寄存器保护命令*/
#define SRAM_LOCK_CMD           (0x76U)
#define SRAM_UNLOCK_CMD         (0x77U)

/* \brief SRAM 索引*/
#define SRAM_SRAMH              (1UL << 2U)                 /* 0x1FFE0000~0x1FFFFFFF, 128KB */
#define SRAM_SRAM123            (1UL << 0U)                 /* SRAM1: 0x20000000~0x2001FFFF, 128KB
                                                             * SRAM2: 0x20020000~0x2003FFFF, 128KB
                                                             * SRAM3: 0x20040000~0x20057FFF, 96KB */
#define SRAM_SRAM4              (1UL << 1U)                 /* 0x20058000~0x2005FFFF, 32KB */
#define SRAM_SRAMB              (1UL << 3U)                 /* 0x200F0000~0x200F0FFF, 4KB */
#define SRAM_SRAM_ALL           (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB)

/* \brief SRAM 访问等待周期*/
#define SRAM_WAIT_CYCLE_0       (0U)                        /* 等待0个CPU周期 */
#define SRAM_WAIT_CYCLE_1       (1U)                        /* 等待1个CPU周期 */
#define SRAM_WAIT_CYCLE_2       (2U)                        /* 等待2个CPU周期 */
#define SRAM_WAIT_CYCLE_3       (3U)                        /* 等待3个CPU周期 */
#define SRAM_WAIT_CYCLE_4       (4U)                        /* 等待4个CPU周期 */
#define SRAM_WAIT_CYCLE_5       (5U)                        /* 等待5个CPU周期 */
#define SRAM_WAIT_CYCLE_6       (6U)                        /* 等待6个CPU周期 */
#define SRAM_WAIT_CYCLE_7       (7U)                        /* 等待7个CPU周期 */

/* \brief SRAM 等待控制寄存器位定义 */
#define SRAMC_WTCR_SRAM123RWT_POS                      (0U)
#define SRAMC_WTCR_SRAM123RWT                          (0x00000007UL)
#define SRAMC_WTCR_SRAM123WWT_POS                      (4U)
#define SRAMC_WTCR_SRAM123WWT                          (0x00000070UL)
#define SRAMC_WTCR_SRAM4RWT_POS                        (8U)
#define SRAMC_WTCR_SRAM4RWT                            (0x00000700UL)
#define SRAMC_WTCR_SRAM4WWT_POS                        (12U)
#define SRAMC_WTCR_SRAM4WWT                            (0x00007000UL)
#define SRAMC_WTCR_SRAMHRWT_POS                        (16U)
#define SRAMC_WTCR_SRAMHRWT                            (0x00070000UL)
#define SRAMC_WTCR_SRAMHWWT_POS                        (20U)
#define SRAMC_WTCR_SRAMHWWT                            (0x00700000UL)
#define SRAMC_WTCR_SRAMBRWT_POS                        (24U)
#define SRAMC_WTCR_SRAMBRWT                            (0x07000000UL)
#define SRAMC_WTCR_SRAMBWWT_POS                        (28U)
#define SRAMC_WTCR_SRAMBWWT                            (0x70000000UL)

/* \brief SRAM 校验状态寄存器位定义 */
#define SRAMC_CKCR_PYOAD_POS                           (0U)
#define SRAMC_CKCR_PYOAD                               (0x00000001UL)
#define SRAMC_CKCR_ECCOAD_POS                          (16U)
#define SRAMC_CKCR_ECCOAD                              (0x00010000UL)
#define SRAMC_CKCR_BECCOAD_POS                         (17U)
#define SRAMC_CKCR_BECCOAD                             (0x00020000UL)
#define SRAMC_CKCR_ECCMOD_POS                          (24U)
#define SRAMC_CKCR_ECCMOD                              (0x03000000UL)
#define SRAMC_CKCR_ECCMOD_0                            (0x01000000UL)
#define SRAMC_CKCR_ECCMOD_1                            (0x02000000UL)
#define SRAMC_CKCR_BECCMOD_POS                         (26U)
#define SRAMC_CKCR_BECCMOD                             (0x0C000000UL)
#define SRAMC_CKCR_BECCMOD_0                           (0x04000000UL)
#define SRAMC_CKCR_BECCMOD_1                           (0x08000000UL)

/* \brief SRAM 寄存器定义*/
typedef struct {
    volatile uint32_t WTCR;
    volatile uint32_t WTPR;
    volatile uint32_t CKCR;
    volatile uint32_t CKPR;
    volatile uint32_t CKSR;
} hc32f4a0_sram_regs_t;

#define HC32F4A0_SRAM    ((hc32f4a0_sram_regs_t *)HC32F4A0_SRAM_BASE)


#ifdef __cplusplus
}
#endif  /* __cplusplus  */

#endif
